module design_main #(
    parameter IMEM_InitEn   = 0,
    parameter IMEM_MEMFILE  = "imageI.txt",
    parameter DMEM_InitEn   = 0,
    parameter DMEM_MEMFILE  = "imageD.txt"

)
(
    input   clk,
    input   rst_n
);


logic   [7:0]       ITCM_addr;
logic   [31:0]      ITCM_data;
logic   [7:0]       DTCM_addr;
logic               DTCM_write;
logic   [31:0]      DTCM_wData;
logic   [31:0]      DTCM_rData;


cpu_top u_cpu_top(
    .clk        (clk        ),
    .rst_n      (rst_n      ),

    .ITCM_addr  (ITCM_addr  ),
    .ITCM_data  (ITCM_data  ),

    .DTCM_addr  (DTCM_addr  ),
    .DTCM_write (DTCM_write ),
    .DTCM_wData (DTCM_wData ),
    .DTCM_rData (DTCM_rData )
);


memory #(
    .InitEn  (IMEM_InitEn  ),
    .MEMFILE (IMEM_MEMFILE )
)
ITCM (
    .clk       (clk       ),
    .Mem_Addr  (ITCM_addr ),
    .Mem_Write (1'b0      ),
    .M_W_Data  (32'b0     ),
    .Mem_Read  (1'b1      ),
    .M_R_Data  (ITCM_data )
);


memory #(
    .InitEn  (DMEM_InitEn  ),
    .MEMFILE (DMEM_MEMFILE )
)
DTCM (
    .clk       (clk        ),
    .Mem_Addr  (DTCM_addr  ),
    .Mem_Write (DTCM_write ),
    .M_W_Data  (DTCM_wData ),
    .Mem_Read  (1'b1       ),
    .M_R_Data  (DTCM_rData )
);


endmodule
